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XRD98L59
CCD Image Digitizers with CDS, PGA and 10-Bit A/D
January 2001-2
FEATURES * 10-bit Resolution ADC * 20MHz Sampling Rate * Programmable Gain: 6dB to 38dB PGA (2x to 80x) * Improved Digitally Controlled Offset-Calibration with Pixel Averager and Hot Pixel Clipper * DNS Filter Removes Black Level Digital Noise * Widest Black Level Calibration Range at Maximum Gain * Manual Control of Offset DAC via Serial Port for Use with High Speed Scanners * 2ns/step Programmable Aperture Delay on SPIX and SBLK * Single 2.7V to 3.6V Power Supply * Low Power for Battery Operation:120mW @ VDD=3V * * * * 5A Typical Stand By Mode Current Three-State Digital Outputs 2,000V ESD Protection 28-pin TSSOP Package
APPLICATIONS * Digital Still Cameras * * * * * * * Digital Camcorders PC Video Cameras CCTV/Security Cameras Industrial/Medical Cameras 2D Bar Code Readers High Speed Scanners Digital Copiers
GENERAL DESCRIPTION The XRD98L59 is a complete low power CCD Image Digitizer for digital, motion and still cameras. The product includes a high bandwidth differential Correlated Double Sampler (CDS), 8-bit digitally Programmable Gain Amplifier (PGA), 10-bit Analog-to-Digital Converter (ADC) and improved digitally controlled black level auto-calibration circuitry with pixel averager hot pixel clipper, and a DNS filter. The Correlated Double Sampler (CDS) subtracts the CCD output signal black level from the video level. Common mode signal and power supply noise are rejected by the differential CDS input stage. The PGA is digitally controlled with 8-bit resolution on a linear dB scale, resulting in a gain range of 6dB to 38dB with 0.125dB per LSB of the gain code. The auto calibration circuit compensates for any internal offset of the XRD98L59 as well as black level offset from the CCD. The PGA and black level auto-calibration are controlled through a simple 3-wire serial interface. The timing circuitry is designed to enable users to select a wide variety of available CCD and image sensors for their applications. The XRD98L59 has direct access to the ADC input for digitizing other analog signals. The XRD98L59 is packaged in 28-lead surface mount TSSOP to reduce space and weight, and is suitable for hand-held and portable applications.
ORDERING INFORMATION
Operating Temperature Range Power Supply -40C to 85C 3.0V Maximum Sampling Rate 20 MSPS
Part No. XRD98L59AIG
Package 28-Lead TSSOP
Rev. 2.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRD98L59
AVDD
VRT AVDD 140 400
VRB 60 AGND
DVDD
OVDD 10
CCDin CDS REFin SPIX SBLK CLAMP CAL Coarse Accumulator Fine Accumulator Internal Clock Generator 10 4-bit CDAC 10-bit FDAC Black Level Offset Calibration Loop Manual DAC Control Hot Pixel Clipper + PGA1 + PGA2 ADCIN OGND 10-bit ADC Reg DB[9:0]
Power Down PD
Offset Calibration Logic Clock Control Calibration Mode SCLK SDI LOAD Serial Interface and Registers Gain Code Target Offset Code Power Down
DNS Filter
+ + -
Pixel Averager
AGND
DGND
Figure 1. XRD98L59 Block Diagram
Rev. 2.00
2
XRD98L59
PIN CONFIGURATION
OVDD DB5 DB6 DB7 DB8 DB9 DVDD DGND SCLK SDI LOAD PD VRT AVDD
! " # $ % & ' ! " & % $ # " ! ' & % $ #
OGND DB4 DB3 DB2 DB1 DB0 SBLK SPIX CLAMP CAL VRB AGND REFin CCDin
28-Lead TSSOP PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol OVDD DB5 DB6 DB7 DB8 DB9 DVDD DGND SCLK SDI LOAD PD VRT AVDD CCDIN REFIN AGND VRB CAL CLAMP SPIX SBLK DB0 DB1 DB2 DB3 DB4 OGND Description Digital Output Power Supply (< AVDD ) ADC Output ADC Output ADC Output ADC Output ADC Output, MSB Digital Power Supply (Must = AVDD ) Digital Ground. Connect to AGND Shift Clock. Latches SDI data on Serial Port Serial Data Input. Serial Port Data Load. Serial Port Power Down, Active High Top ADC Reference. Sets full scale of ADC Analog VDD CDS inverting input. Connect through capacitor to CCD signal Reference input (CDS non inverting input). Connect through capacitor to CCD Ground Analog Ground Bottom ADC Reference. Sets zero for ADC. Optical Black (OB) Clamp CDS DC Restore Clamp Sample Video Pixel (CDS Clock) Sample Black Reference (CDS Clock) ADC Output, LSB ADC Output ADC Output ADC Output ADC Output Digital Output GND. Connect to AGND
Rev. 2.00
3
XRD98L59
XRD98L59
DC ELECTRICAL CHARACTERISTICS - XRD98L59 Unless otherwise specified: OVDD = DVDD = AVDD = 3.0V, Pixel Rate = 20MSPS, TA = 25C
Symbol Parameter Min. Typ. Max. Unit Conditions
CDS Performance CDSVIN VDARK r ON AVMIN AVMAX PGA n Input Range Maximum Dark Voltage Offset CLAMP On Resistance 150 120 800 mV PP mV Pixel (VBlack - VVideo), (See Figure 2) At any gain. (See Figure 2)
PGA Parameters Minimum Gain Maximum Gain Resolution 3.5 5 36 8 6.5 dB dB bits Transfer function is linear steps in dB (1LSB = 0.125dB)
ADC Parameters (Measured in ADCIN Test Mode), SDI = 0100 0000 0101 b ADC n fs DNL EZS EFS VIN Resolution Max Sample Rate Differential Non-Linearity Zero Scale Error Full Scale Error DC Input Range GND 10 20 -1 +0.75 +25 1.5 AVDD 1.5 bits MSPS LSB mV % FS V AVIN of the ADC can swing from AGND to AVDD. Input range is limited by the output swing of the PGA. Measured relative to VRB
VREF
ADC Reference Voltage
2
V
VRB VRT
Self Bias VRB Self Bias VRT
( (
VRB = AVDD
10 VRB = AVDD 1.30
) )
0.2
0.3
0.4
V
2.0
2.3
2.6
V
Rev. 2.00
4
XRD98L59
DC ELECTRICAL CHARACTERISTICS - XRD98L59 (CONT'D) Unless otherwise specified: OVDD = DVDD = AVDD = 3.0V, Pixel Rate = 20MSPS, TA = 25C
Symbol Parameter Min. Typ. Max. Unit Conditions
System Specifications DNL S INLSMIN INLSMAX en MAXAV en MINAV System DNL System INL @ Minimum Gain System INL @ Maximum Gain Input Referred Noise @ Max Gain Input Referred Noise @ Min Gain Latency Digital Inputs VIH VIL IL C IN Digital Outputs VOH V OL IOZ Digital Output High Voltage Digital Output Low Voltage High-Z Leakage -10
OVDD-0.5
-1
+0.75 1.5 2 2 0.2
LSB LSB LSB mVrms mVrms
No missing codes, monotonic INL error is dominated by CDS/PGA linearity INL error is dominated by CDS/PGA linearity Gain Code = FFh Gain Code = 00h
0.7
Pipeline Delay
4
cycles
Digital Input High Voltage Digital Input Low Voltage DC Leakage Current Input Capacitance
2.1 0.5 5 5
V V A pF VIN = GND or VDD
V 0.5 10 V A
While sourcing 2mA While sinking 2mA OE = 0 or PD = 1 Output = OGND or ODVDD
Rev. 2.00
5
XRD98L59
DC ELECTRICAL CHARACTERISTICS - XRD98L59 (CONT'D) Unless otherwise specified: OVDD = DVDD = AVDD = 3.0V, Pixel Rate = 20MSPS, TA = 25C
Symbol Parameter Min. Typ. Max. Unit Conditions
Digital I/O Timing tDL tPW1 tPW2 tPIX t BK tVD t SCLK tSET tHOLD t L1 t L2 Power Supplies AVDD DVDD OVDD IDD IDDPD Analog Supply Voltage Digital Supply Voltage Digital Output Supply Voltage Supply Current Power Down Supply Current 2.7 2.7 2.7 3.0 3.0 3.0 40 5 3.6 3.6 3.6 55 25 V V V mA A Set DVDD = AVDD OVDD < AVDD OVDD = AVDD = DVDD =3.0V, Includes Reference Current PD = 1, Clocked Data Valid Delay Pulse Width of SPIX Pulse Width of SBLK Pixel Period Sample Black (SBLK), Aperture Delay Sample Video (SPIX), Aperture Delay Shift Clock Period Shift Register Setup Time Shift Register Hold Time Load Set-up Time Load Hold Time 10 10 10 0 10 10 50 3.5 2.7 100 28 35 ns ns ns ns ns ns ns ns ns ns ns SBLK Delay = 000 SPIX Delay = 000
Rev. 2.00
6
XRD98L59
VBlack
VDark
CCD Waveform
VVideo
CDS Vin
Figure 2. Definition of terms for VOut of the CCD waveform: CDSVIN = (VBlack - VVideo)
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3 VDD to GND ..................................................... +7.0V VRT & VRB .................................... VDD +0.5 to GND -0.5V VIN ................................................... VDD +0.5 to GND -0.5V All Inputs .............................. VDD +0.5 to GND -0.5V All Outputs ............................ VDD +0.5 to GND -0.5V Storage Temperature .......................... -65C to 150C Lead Temperature (Soldering 10 seconds) ..... 300C Maximum Junction Temperature .................... 150C Package Power Dissipation Ratings (TA= +70C) TSSOP ....................................... GJA = 90C/W ESD ........................................................ 2000V
Notes:
1
Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. VDD refers to AVDD, OVDD and DVDD. GND refers to AGND, OGND and DGND.
2
3
Rev. 2.00
7
XRD98L59
SERIAL INTERFACE The XRD98L59 uses a three wire serial interface (LOAD, SDI & SCLK) to access the programmable features and controls of the chip.The serial interface uses a 12-bit shift register. The first 4 bits shifted in are the address bits, the next 8 bits are the data bits. The address bits select which of the internal registers will receive the 8 data bits. There is no checking or read back of the address bits to ensure a valid register is written to. If the address bits select an undefined register, the data will be discarded. SERIAL PORT PROCEDURES 1) Set LOAD pin low to enable shift register. 2) Shift in 4 address bits (msb first), followed by 8 data bits (msb first). 3) Set LOAD pin high to transfer data from the shift register to the serial interface register array. For optimum image quality, do not run the serial port during active video. Serial port clocking can couple into the signal path and degrade accuracy. Also, do not continuously run SCLK. Reseting the XRD98L59 is recommended after initial power-up. It is generally good practice to reset the XRD98L59 because the serial data may be forced to an unknown state during power supply cycling by the digital ASIC.
LOAD tL 1 SCLK t set SDI
A3 A2
tS C L K
tL 2
thold
A1 A0
MSB D7 D6 D5 D4 D3 D2 D1
LSB D0
t1
t2
...
t11
t12
Time
Figure 3. Serial Interface Timing Diagram
Rev. 2.00
8
XRD98L59
LSB SDI D0 SCLK D1 D2
Data Bits
MSB
Address Bits
D3
D4
D5
D6
D7
A0
A1
A2
A3
LOAD data input
Register Array register select Address Decoder
Figure 4. Serial Interface Timing Diagram
Reg. Name Gain Target Offset Delay Clock Control Calibration FDAC (msb) FDAC (lsb) CDAC * * * Reset
Address bits A3 A2 A1 A0 0 0 00 0 0 01 0 0 10 0 0 11 0 1 00 0 1 01 0 0 1 1 1 0 1 1 0 0 1 0
D7
Data bits D3 D2 D1 D0 [7:0] Offset [5:0] SBLK delay [2:0] SPIX delay[2:0] Exar test RST rej Exar test Clamp opt SBLK pol SPIXpol Clamp pol CAL pol Delay test ADCIN PD OE Cal Hold Speed Up DNS 1 DNS 0 Man DAC FDAC [9:2] FDAC [1:0] CDAC [3:0] D6 D5 D4 Gain Not Used
1
1
1
1
Reset
Table 1. Serial Interface Register Address Map
Rev. 2.00
9
XRD98L59
D7 D6 D5 Gain[7:0] 0 0 0 0 0 0 0 0 minimum gain (6 dB) * 1 1 1 1 1 1 1 1 maximum gain (38 dB) D4 D3 D2 D1 D0
Table 2. Gain Register bit assignment (Address 0000)
D7 not used D6 not used D5 Offset[5:0] 000000 000001 000010 100000 111111 D4 Do not use (00h) Do not use (01h) minimum offset (02h) default offset (20h) * maximum offset (3Fh) D3 D2 D1 D0
Table 3. Target Offset Register bit assignment (Address 0001) for PGA
D7 SBLK delay[2:0] 0 0 0 min delay * 1 1 1 max delay
D6
D5
D4 SPIX delay[2:0] 0 0 0 min delay * 1 1 1 max delay
D3
D2
D1
Exar test
D0
0 0 default 01, 10, 11 do not use
Table 4. Delay Register bit assignment (Address 0010)
D7 not used D6 RST rej 0 switch ON* 1 clocked D5
Exar test
0 default 1 do not use
D4 D3 D2 D1 D0 CLAMP opt SBLK pol SPIX pol CLAMP pol CAL pol 0 Cal only 0 active low* 0 active low* 0 active low* 0 active low* 1 Clamp+Cal* 1 active high 1 active high 1 active high 1 active high
Table 5. Clock Register bit assignment (Address 0011) for SPIX or SBLK
D7 not used
D6 not used
D5 not used
D4 not used
D3 Delay test 0 test off * 1 test on
D2 ADCIN 0 test off * 1 test on
D1 D0 PD OE 0 outputs off 0 convert * 1 power down 1 outputs on *
Table 6. Control Register bit assignment (Address 0100)
D7 not used D6 not used D5 not used D4 Cal Hold 0 cal active* 1 hold value D3 Speed Up 0 Speed Up off 1 Speed Up on* D2 DNS1 0 DNS off 1 DNS on* D1 D0 DNS0 Man DAC 0 = Wide* 0 automatic* 1 = Narrow 1 manual
Table 7. Calibration Register bit assignment (Address 0101)
Note: * Shading indicates default values after power up or reset. The XRD98L59 does not reset the registers to default value after PD.
Rev. 2.00
10
XRD98L59
D7 D6 FDAC[9:2] 1 1 1 1 1 1 1 1 max pos offset 1 0 0 0 0 0 0 0 zero offset 0 0 0 0 0 0 0 0 max neg offset * D5 D4 D3 D2 D1 D0
Table 8. FDAC (MSB) Register bit assignment (Address 0110)
D7 not used D6 not used D5 not used D4 not used D3 not used D2 not used D1 D0 FDAC[1:0] 1 1 max pos offset 0 0 max neg offset *
Table 9. FDAC (LSB) Register bit assignment (Address 0111)
D7 not used
D6 not used
D5 not used
D4 not used
D3 1111 1011 0000
D1 CDAC[3:0] max pos offset +50 mV zero offset max neg offset * -137.5 mV
D2
D0
Table 10. CDAC Register bit assignment (Address 1000)
D7 not used
D6 not used
D5 not used
D4 not used
D3 not used
D2 not used
D1 not used
D0 Reset 0 normal * 1 reset chip
Table 11. Reset Register bit assignment (Address 1111)
Note: * Shading indicates default values after power up or reset. The XRD98L59 does not reset the registers to default value after PD.
Rev. 2.00
11
XRD98L59
CORRELATED DOUBLE SAMPLE/HOLD (CDS) The function of the CDS block is to sense the voltage difference between the black level and video level for each pixel. The PGA then amplifies this difference to the desired level for the ADC. The CDS and PGA are fully differential. The PGA output is converted to a single ended signal and fed to the ADC. The CCDin pin (CDS inverting input) should be connected, via a capacitor, to the CCD output signal. The REFin pin (CDS noninverting input) should be connected, via a capacitor, to the CCD "Common" voltage. This is typically the CCD Reference output or ground. At the beginning (or end) of every video line, the DC restore switch forces one side of the external capacitors to an internal Vbias1 level (approximately 0.8V). The DC restore switch is controlled by the combination of the CLAMP signal ANDed with the 2 clock. (See Figure 5). During the black reference phase of each CCD pixel the 1 (Sample Black Reference) switches are turned on, shorting the PGA1 inputs to a second bias level. The Coarse Offset DAC adds an adjustment to the Vbias2 level to cancel offset in the CCD signal. When the 1 switches turn off, the pixel black reference(VBLACK) is sampled on the internal reference sample capacitors, and the PGA is ready to gain up the CCD video signal. During the video phase of each CCD pixel the difference between the pixel black reference level and video level is transmitted through the internal reference sample capacitors and converted to a fully differential signal by the PGA1 amplifier. At this time the 2 (Sample Pixel value) switches turn on, and the internal video sample capacitors track the amplified difference.
XRD98L59 Vbias2 CDS External DC blocking capacitors Reset reject switches CCD CCDin PGA1 REFin Internal black sample capacitors (~5PF) PGA2 To ADC PGA
1
Coarse Offset DAC
Fine Offset DAC
2
AGND
rO N 1 2 0
CLAMP 2 DC restore switches Vbias1~0.8V
Internal video sample capacitors (~5PF)
Figure 5. Block Diagram of CDS and PGAs
Rev. 2.00
12
XRD98L59
PIXEL TIMING SBLK & SPIX The timing required by the XRD98L59 to sample individual pixel data from a CCD output is shown below in Figure 6. The diagram shows the general relationship of timing signals SBLK and SPIX to the CCD waveform.
tPIX Pixel N Reset Phase Black Reference Phase Reset Reject Switch Closed tBK CCDIN tRST RST REJ* 1 2 pixel black level sample point tVD pixel video level sample point 1 Video Phase Pixel N + 1
The XRD98L59 was designed to sample any analog CCD waveform. In order to do this the timing signals need to be referenced to the waveform itself, not to the CCD's timing generator.
Reset Reject Switch Open
Reset Pulse
tPW2 2
3 SBLK 5 SPIX DB[9:0] N-4
tPW1 4
3 5 4
N-3 tDL tDL
Figure 6. CDS Timing Diagram - Proper Placement of Timing is Critical to Image Quality, SDI=0011 0100 1100 *RST REJ is an internally generated signal.
Event 1 2 3 4 5
RSTREJ RSTREJ
SBLK High SPIX High
Action Disconnects CDS Inputs from Reset Noise Connects CDS Inputs
Sample Black Level Sample Video Level SBLK/SPIX Low Hold Video and Black Level
Table 12. Event Table for CDS Timing (SDI=0011 0100 1100)
Rev. 2.00
13
XRD98L59
RSTREJ reduces CCD reset noise by disconnecting the input of the XRD98L59 from the CCD during the CCD reset pulse. RSTREJ is an internally generated signal. RSTREJ disconnects the input after the SPIX and before the SBLK sampling events to reject CCD reset noise. The RSTREJ switch is always closed (the input is always connected) if D6=0 in the clock register (address 0011) of the serial port. For the timing example shown in Figure 6, SBLK high samples the pixel black level. The actual hold point of the pixel black level occurs after a delay of tBK. tBK is the aperture delay of the SBLK timing signal. The polarities of the SBLK and SPIX signals are independently programmable via the serial port. For the timing example shown in Figure 6, SPIX high samples the pixel video level. The actual hold point of the pixel video level occurs after a delay of tVD. tVD is the aperture delay of the SPIX timing signal. The polarity of the SPIX signal is serial port programmable. The function of the CDS block, shown in Figure 7, is to sense the voltage difference between the black level and video level for each pixel. The CDS and PGA are fully differential to reject common mode noise. The PGA output is converted to a single ended signal, and then fed to the ADC. REFIN (CDS non-inverting input) should be connected, via a capacitor, to the CCD "Common" voltage. This is typically CCD ground. CCDIN (CDS inverting input) should be connected, via a capacitor, to the CCD output signal. The external coupling capacitors on CCDIN and REFIN should be of equal values to minimize gain errors (typically 0.01f +/-10%).
VBIAS2 External Coupling Capacitors C Vout C D GND
Gain Register 2 C1 C2 + PGA1 C3 C4 + PGA2 + BUF to ADC
1 RSTREJ
CLAMP
Vbias1 ~0.8
Figure 7. Block Diagram of the CDS, Reset Phase: RSTREJ Switch is Open
Rev. 2.00
14
XRD98L59
During the reset phase of each pixel the RSTREJ switches are turned off, see Figure 7, opening the XRD98L59 CDS input. This is done to limit reset pulse transients seen by the front end of the XRD98L59. During the black reference phase of each pixel the RSTREJ switches are closed, allowing the difference between the black reference level voltage and VBIAS2 to develop across capacitors C1 and C2 (see Figure 8). 1 is closed when SBLK is active.
VBIAS2 External Coupling Capacitors In_Pos C Vout C D GND In_Neg
Gain Register 2 C1 C2
1 RSTREJ + PGA1 -
+ PGA2 C3 C4
+ BUF to ADC
CLAMP
Vbias1 ~0.8
Figure 8. CDS - Black Reference Phase: RSTREJ and 1 Switch Closed During the video phase of each pixel the 2 switches are closed when SPIX is active. The difference between the pixel black reference level and video level is transmitted through capacitors C1 & C2. Differential amplifier PGA1
VBIAS2 External Coupling Capacitors C Vout C D GND
amplifies both CDS inputs from CCDIN and REFIN. The inactive phase of SPIX turns off the 2 switches, storing the differential pixel value on capacitors C3 & C4 (see Figure 9).
Gain Register 2
1 RSTREJ C1 C2 + PGA1 -
+ PGA2 C3 C4
+ BUF to ADC
CLAMP
Vbias1~0.8
Figure 9. CDS - Video Phase: 1 Switches Open, 2 and RSTREJ Switches Closed
Rev. 2.00
15
XRD98L59
Black Reset Reference Video Phase Phase Phase
CCD
SBLK
SPIX
DB[9:0]* (Internal Signals) RSTREJ
1
2 ADCLK
HOLD
TRACK
Figure 10. Timing Diagram of the CDS Clocks and Internal Signals (RSTREJ, 1, 2, ADCCLK) , ) SDI = 0011 0100 1100 * Digital Output Data is Updated on the Falling Edge of 2. This Update Position is Affected by the Aperture Delay of 2.
Note: Aperture Delay is not Shown Rev. 2.00
16
XRD98L59
SBLK and SPIX Programmable Aperture Delay (SDI Address = 0010)
The positioning of 1 and 2 from Figure 10, are optimized by using a programmable aperture delay function. 1 and 2 are delayed internally by the amount specified in the serial port. SBLK delay (D7:D5) delays the 1 clock and SPIX delay (D4:D2) delays the 2 clock. The delay is 2ns per lsb. The aperture delays tBK and tVD are added to the programmable aperture delay to determine final positioning. The tables below include the tBK and tVD aperture delays.
D7 0 0 0 0 1 1 1 1
D6 0 0 1 1 0 0 1 1
D5 0 1 0 1 0 1 0 1
1 Aperture Delay
3.5ns (default) 5.5ns 7.5ns 9.5ns 11.5ns 13.5ns 15.5ns 17.5ns
D4 0 0 0 0 1 1 1 1
D3 0 0 1 1 0 0 1 1
D2 0 1 0 1 0 1 0 1
2 Aperture Delay
2.7ns (default) 4.7ns 6.7ns 8.7ns 10.7ns 12.7ns 14.7ns 16.7ns
Table 13. Programmable 1 Delays
Table 14. Programmable 2 Delays
The aperture delay of 2 also delays the output data bus DB[9:0]. Digital output data is updated on the falling edge of 2 as shown in Figure 10. Data is valid after tDL
plus the change in 2 aperture delay. For example, if D[4:2] equals 001b, then data is valid at tDL + 2ns. (t DL is shown in Figure 6).
Rev. 2.00
17
XRD98L59
LINE CALIBRATION MODE Line calibration mode calibrates during the OB pixel output from the CCD at the end of every line. Figure 11, shows the outline of a typical CCD area array. The active (white) pixels are shown with the OB (shaded) pixels around the edges. The OB pixels used in line calibration are identified below in Figure 11 as the dark shaded OB pixels on the right hand side of the array.
Active Pixels
End of LIne OB Calibration Pixels
Figure 11. End of Line OB Pixels Used for Line Calibration Mode on a Typical CCD Array
Most timing generators (TG's) have signals that define the start of line and end of line OB pixels on the CCD array. CAL should always be active on start or the end of line that defines the greatest number of OB pixels possible. The more OB pixels that the XRD98L59 can use for its auto-calibration, the faster it can achieve and maintain calibration. CAL and CLAMP must never be active at the same time. CLAMP is used to set the input DC bias voltage. (See Figure 5).
Line Timing: CLAMP and CAL CLAMP & CAL Line Timing (SDI address = 0011, D4 = 1)
The timing needed for Line Calibration Mode is shown in Figure 12. The timing signal CAL gates the XRD98L59's auto-calibration logic. CAL is active during the end of line OB pixels.
Rev. 2.00
18
XRD98L59
Line N Active Video pixels Vertical Shift (Horizontal Clocking Off)
Line N+1 Dummy & OB* pixels Active Video pixels
OB* pixels
CCD Signal CAL CLAMP
Min 1 Pixel Min 1 Pixel * Note: OB = Optically Black or Shielded pixels.
Figure 12. Example of CLAMP & CAL Line Calibration Mode Timing (CAL and CLAMP Polarity are Serial Port Programmable) SDI = 0011 0001 0011
Line Timing: CAL Only CAL Only Line Timing (SDI address = 0011, D4 = 0)
The timing needed for "CAL Only" Line Calibration Mode is shown in Figure 13. In "CAL Only" Line Calibration the timing signal CAL has two functions, DC Clamping of the CCDIN and REFin inputs and gating the auto-calibration logic. Using "CAL Only" Line Timing enables the designer to eliminate the requirement of providing a CLAMP Timing signal to the XRD98L59.
Rev. 2.00
19
XRD98L59
End of Line N Start of Line N+1
Active Video Pixels
OB Pixels
Vertical Shift
Dummy & OB Pixels
Active Video Pixels
CCD Signal t C A L (min 5 Pixels)
CAL
Internal DC R e s t o r e T i m e Internal Black Level Calibration T i m e
4 Pixels
t C A L - 4 Pixels
(D1 = 0) CLAMP
Figure 13. Example of Minimum Timing Requirements for CAL Only Line Calibration Mode (CAL and CLAMP Polarity are Serial Port Programmable) SDI = 0011 0000 0000 Most timing generators (TG's) define the start of line and end of line OB pixels on the CCD array. The CAL timing signal should always be active for the greatest number of OB pixels possible, either during start or end of line. The more OB pixels that the XRD98L59 can use for its autocalibration, the faster it can achieve and maintain calibration. While in "CAL ONLY" Line Calibration Timing Mode, CLAMP needs to be held inactive during the output of active video and OB pixels from the CCD. Figure 13 shows the minimum timing requirements for the "CAL ONLY" Line Calibration Timing Mode. The inactive state for CLAMP depends on the CLAMP-Polarity setting (Clock Reg bit D1).
Vertical Shift Reject
The CLAMP input can be used to implement a Vertical Shift Reject function while in "CAL ONLY" Line Calibration Timing Mode. The Vertical Shift Rejection, also called preblanking, can be used to reject and any large transients present in the CCD output during the vertical clocking. To implement the Vertical Shift Reject (Preblanking) function on the XRD98L59 the CLAMP opt bit must be low (Clock Reg D4=0) and the CLAMP input driven with the preblanking timing signal. The preblanking timing signal, commonly called PBLK, is generated by the system timing generator and defines the vertical shift of the CCD (see Figure 13a). The preblanking pulse opens the Reset Reject Switches internal to the XRD98L59, see Figure 5, thereby rejecting any transients in the CCD output while the vertical shifting is being done.
Rev. 2.00
20
XRD98L59
End of Line N Start of Line N+1
Active Video Pixels
OB Pixels
Vertical Shift
Dummy & OB Pixels
Active Video Pixels
CCD Signal t C A L (min 5 Pixels)
CAL Internal DC Restore Time
4 Pixels
Internal Black Level Calibration T i m e (D1 = 0) CLAMP
t C A L - 4 Pixels
Figure 13a. Example of Vertical Shift Reject Timing using the CLAMP input while in "CAL ONLY" Line Calibration Mode. (CAL and CLAMP Polarity are Serial Port Programmable) SDI = 0011 000 0000 PROGRAMMABLE GAIN AMPLIFIER (PGA) PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x, and 6.25x). The gain transitions occur at PGA gain codes 64d and 128d (40h & 80h). PGA2 provides gain from 6dB to 22dB (2x to 12.5x) with 0.125dB steps. The combined PGA blocks provide a programmable gain range of 32dB. The minimum gain (code 00h) is 6dB. The maximum gain (code FFh) is 38dB. The following equation can be used to compute PGA gain from the gain code: Figure 10). The ADC tracks the output of the PGA while ADCLK is high and holds when ADCLK is low. This allows maximum time for the PGA output to settle to its final value before being sampled. The conversion is then performed and the parallel output is updated, after a 2.5 cycle pipeline delay, on the edge of 2. The pipeline delay of the entire XRD98L59 is 4 clock cycles. The ADC reference levels, VRT & VRB, are set by an internal resistor divider between VDD and GND. The divider provides VRB=VDD/10 and VRT=VDD/1.3. To maximize the performance of the XRD98L59, VRT & VRB should have high frequency by-pass capacitors to AGND. The value of these by-pass capacitors will affect the time required for the reference to charge up and settle after power down mode. Using 0.01uF capacitors will give about 40 s settling time for full accuracy. The ADC output bus is equipped with a high impedance capability which is controlled by OE bit in the serial interface control register. The outputs are enabled when the OE bit is high, and go into high impedance mode when the OE bit is low.
ae Code o Gain[dB] = 6 + c 32 / e 256 o
where Code is the 8 bit value (0 to 255) programmed in the serial interface Gain register. Due to device mismatch the gain steps at codes 63 - 64 and 127 128 may not be monotonic. ANALOG TO DIGITAL CONVERTER (ADC) The analog-to-digital converter is based upon a two-step sub-ranging flash converter architecture with a built in track and hold input stage. The ADC conversion is controlled by an internally generated signal, ADCLK (see
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XRD98L59
The ADC input node can be accesed for test purposes using the ADCIN mode (SDI address 0100). Use the following procedure to enable the ADCIN mode: 1) In the Serial interface Clock register, set the Clamp Opt bit low (D4). 2) In the Serial interface Control register, set the ADCIN bit high (D2). 3) Clock SBLK & SPIX to generate internal ADC_CLK signal. 4) Apply ADC input signal to CCDin. In this test mode the analog signal, Vin, applied to CCDin pin will be converted by the ADC. The ADC output code is related to Vin by the following rules: 1) For Vin < VRB, ADC output code = 0, 2) For Vin > VRT, ADC output code = 1023, 3) For VRB < Vin < VRT, ADC output code = 1024 x (Vin - VRB) / (VRT - VRB) CONTROL & RESET REGISTERS
PD Bit (Power Down)
This bit is used to put the chip in the Power Down mode. It has the same effect as the PD pin. When the PD bit is high the chip will go into the power down mode, all conversions stop. When the PD bit is low the chip is in its normal active mode. In the Power Down mode the digital output pins are forced to the high impedance mode and the ADC reference is disconnected. The serial interface pins remain active in the Power Down mode.
OE Bit (Output Enable)
The ADC digital output bus is equipped with a high impedance capability. When the OE bit is high the digital outputs are enabled (active). When the OE bit is low the digital outputs are in the high impedance mode (not active). The OE bit only controls the digital output drivers, all other circuits on the chip will remain active.
RESET Bit
This bit is used to reset all internal registers to default values. This includes all the serial interface registers as well as the registers in the calibration logic. To reset the chip write a "1" to the reset bit. The reset bit will clear itself after an internal delay, so there is no need to write a "0" to the reset bit. The chip also has a Power-On-Reset function (POR) so it will always power up with default values in all registers. It is recommended that the XRD98L59 be reset after power is cycled to avoid loading potentially incorrect serial port data from other ASICs in the system.
ADCIN Bit
This bit activates a switch that connects CCDin directly to the ADC input. In this mode, the PGA output is disabled. See the ADC section for details.
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XRD98L59
BLACK LEVEL OFFSET CALIBRATION
CCD Signal
10 CDS + 2/) + 2/) 10-bit ADC Reg DB[9:0]
4-bit
CDAC
10-bit
FDAC Black Level Offset Calibration Loop
10
ManDAC CDAC, FDAC
Hot Pixel Clipper
Coarse Accumulator
Fine Accumulator
From Serial Interface Registers CalHold, SpeedUp Gain Code DNS Target Offset Code
Offset Calibration Logic
DNS Filter
+ +
Pixel Averager
-
Figure 15. Black Level Offset Calibration Block Diagram
To get the maximum color resolution and dynamic range, the XRD98L59 uses a digitally controlled feedback circuit to correct for offset in the CCD signal as well as offset in the CDS, PGA & ADC signal path. This calibration is
done while the CCD outputs Optical Black (OB) pixels. The CAL input signal is used to define when the CCD output contains OB pixels. The calibration logic will take into account the internal pipeline delay.
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XRD98L59
Hot Pixel Clipper
1.4
CCD's occasionally have hot pixels. These are defective pixels which always output a bright level. To ensure the Black Level is not significantly affected by hot pixels in the OB area, the Hot Pixel Clipper limits pixel data from the ADC to a maximum value of 127 (7Fh). The Hot Pixel Clipper is only active when CAL is active. This clipping only affects the data used by the internal calibration logic. Data on the digital output bus DB[9:0] is not clipped.
VDD = 3.0V 1.2 1.0 ADC LSBs 0.8 0.6 0.4 0.2 0.0 0 64 128 PGA Code 192 256
Pixel Averager
After the clipper, the logic takes the average of the Optical Black pixels defined by CAL. This averaging function filters noise.
Figure 16. XRD98L59 Offset DAC Step Size in ADC Output LSBs CALIBRATION OPTIONS
Offset Difference Using the Target Offset Register
The Target Offset register (Address 0001) value (6 lsb's) is subtracted from the OB pixel average. If the difference is positive, the offset DACs are decremented to reduce the effective ADC output code. If the difference is negative, the offset DACs are adjusted to increase the effective ADC output code. The amount of adjustment is shown in Figure 16. Set the Target Offset Register value equal to the desired black level output code. For example: Set Target Offset Register to code 32 and black CCD outputs are nominally output as 32. Default is code 32 decimal.
Speed Up Mode
The purpose of this option is to reduce the amount of time required for initial convergence of the calibration feedback system. The feedback system is designed to have a slow response time to avoid introducing image artifacts. The slow response time is achieved by limiting the Fine accumulator changes to 1 count at a time. The Speed Up option maintains this slow response while the difference between the averaged ADC data and the Target Offset Code is small. But when the difference is larger than 32 lsb's the Fine accumulator takes large steps. The actual step size depends on the Gain code, and is set such that the step will cause no more than a 32 LSB change in the ADC output. To activate the Speed Up mode write a 1 to the SpeedUp bit in the Calibration register (bit D3 of Serial Interface Register #5). By default the SpeedUp mode is active.
Coarse & Fine Accumulators
The Coarse and Fine Accumulators are the registers which hold the digital codes for the Coarse and Fine Offset DACs. The Offset DAC adjustments are made by adding or subtracting to the value in the Fine Accumulator. If there is an overflow or underflow in the Fine Accumulator, the Fine Accumulator is reset to it's midscale value, and the Coarse Accumulator is incremented or decremented accordingly.
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XRD98L59
Digital Noise Supression (DNS Filter)
To activate the DNS mode, a "1" is written to DNS1 bit in the Calibration register (bit D2 of Serial Interface Register #5). By default the DNS mode is active. In DNS mode, the user has the option to select narrow band or wide band Noise Suppression Filters by setting DNS0 bit to a "1" (narrow) or "0" (wide) respectively. Best performance is achieved by setting DNS1 = "1" and DNS0 = "0". To activate the Hold mode write a 1 to the CAL Hold bit in the Calibration register (bit D4 of Serial Interface Register #5). By default the Hold mode is not active.
Manual Mode
The purpose of this mode is to disable the automatic calibration feature. In the Manual mode, the Coarse accumulator is programmed by writing to the CDAC register, the Fine accumulator is programmed by writing to the FDAC register. The Fine accumulator is a 10 bit register, but the Serial interface registers are only 8 bits wide. As shown in the Serial Interface Register Address Map, two serial interface registers are concatenated to provide 10 bits to the Fine accumulator. To activate the Manual mode write a 1 to the ManDAC bit in the Calibration register (bit D0 of Serial Interface Register #5). By default the Manual mode is not active.
Hold Mode
The purpose of this mode is to prevent any changes in the Fine or Coarse accumulators. The idea is to first run the calibration normaly so the Fine and Coarse accumulators converge on the programmed Target Offset Code. Then, just before acquiring the final image data, activate the Hold mode. This will ensure the black level offset of the CDS/PGA does not change while the final image is being transferred out of the CCD. Once the image has been acquired from the CCD, turn off the Hold mode so the chip can continue to compensate for any changes in offset due to temperature drift or other effects.
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XRD98L59
Serial Ports
Rev. 2.00
VRT AVDD
AVDD
ASIC/DSP
OVDD DB5 DB6 DB7 DB8 DB9 DVDD DGND SCLK SDI LOAD PD
12V
AVDD
AVDD
5 6 7 8 9 10 11 12 13 14
1 2 3 4
0.1F
XRD98L59
10-Bit Digital Video Input
26
5-10
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CCD
0.01F
OGND DB4 DB3 DB2 DB1 DB0 SBLK SPIX CLAMP CAL VRB AGND REFin CCDin
3
4-6 V Driver
3
0.01F
0.1F
Timing Generator
CLOB CLDM SHD SHP
Figure 17. Application Diagram; ASIC with External Timing Generator
Serial Port
Rev. 2.00
VRT AVDD
AVDD
ASIC/DSP
OVDD DB5 DB6 DB7 DB8 DB9 DVDD DGND SCLK SDI LOAD PD
12V
AVDD
AVDD
5 6 7 8 9 10 11 12 13 14
3 4
1 2
0.1F
XRD98L59
10-Bit Digital Video Input
27
CCD 4-6 V Driver 3
5-10 0.01F
28 27 26 25 24 23 22 21 20 19 18 17 16 15 SPIX CLAMP CAL VRB AGND REFin CCDin OGND DB4 DB3 DB2 DB1 DB0 SBLK
0.01F
0.1F
XRD98L59
Intenal Timing Generator
Figure 18. Application Diagram; ASIC with Internal Timing Generator
XRD98L59
36 34 32 30 28 26
PGA Gain (dB)
24 22 20 18 16 14 12 10 8 6 4 0 20 40 60 80 100 120 140 160 180 200 220 240 255
Gain Code
Figure 19. PGA Gain vs. Gain Code
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XRD98L59
46
44
42
IDD (AVDD + DVDD) (mA)
40
38
VDD = 3.0V
36
34
32
30 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
Sampling Frequency (MHz)
Figure 20. IDD vs Sample Rate
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XRD98L59
70
65
60
SNR (dB)
55
50
45
40
35
30 0 63 64 127 128 255
Gain Code
Figure 21. Typical SNR vs Gain at 20MHz Sample Rate SNR = 20 log (Full scale voltage/rms noise)
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XRD98L59
0.8
0.6
0.4
0.2 LSB 0 -0.2 -0.4 -0.6 0 128 256 384 512 CODE 640 768 896 1024
Figure 22. ADC Only DNL
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XRD98L59
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32
Figure 23. XRD98L59 1.45 Mpixel Camera Reference Schematic (Sheet 1)
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XRD98L59
Figure 24. XRD98L59 1.45 Mpixel Camera Reference Schematic (Sheet 2)
XRD98L59
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34
Figure 25. XRD98L59 2.31 Mpixel Camera Reference Schematic (Sheet 1)
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XRD98L59
Figure 26. XRD98L59 2.31 Mpixel Camera Reference Schematic (Sheet 2)
XRD98L59
28 LEAD THIN SHRINK SMALL OUTLINE (4.4mm TSSOP)
Rev. 2.00
D
28
15
E
1 14
H
C A2 Seating Plane e B A1 L A
SYMBOL A A1 A2 B C D E e H L
INCHES MIN MAX 0.033 0.047 0.002 0.006 0.031 0.041 0.007 0.012 0.004 0.008 0.378 0.386 0.169 0.177 0.0256 BSC 0.248 0.256 0.018 0.030 0 8
MILLIMETERS MIN MAX 0.85 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.80 4.30 4.50 0.65 BSC 6.30 6.50 0.45 0.75 0 8
Note: The control dimension is in millimeter column
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XRD98L59
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet January 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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